a design technique for adapting number and boundaries of reconfigurable modules at runtime设计技术适应数量和可重构模块在运行时的边界.pdfVIP

Hindawi Publishing Corporation International Journal of Reconfigurable Computing Volume 2009, Article ID 942930, 10 pages doi:10.1155/2009/942930 Research Article A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime Thilo Pionteck, Roman Koch, Carsten Albrecht, and Erik Maehle Institute of Computer Engineering, University of Lubeck, 23538 Lubeck, Germany ¨ ¨ Correspondence should be addressed to Thilo Pionteck, pionteck@iti.uni-luebeck.de Received 30 November 2008; Accepted 17 May 2009 Recommended by Michael Huebner Runtime reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a changing number of processing units mapped onto diverse locations. Design tools should support an arbitrary placement of processing modules and the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules. While few works address the design of flexible system architectures, the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules is hardly ever considered due to design tool limitations. In this paper, a technique for circumventing this restriction is presented. It allows for a rededication of the reconfigurable area to a different number of individually sized reconfigurable regions. This technique is embedded in the design flow of a runtime reconfigurable system architecture for Xilinx Virtex-4 FPGAs. The system architecture will also be presented to provide a realistic application example. Copyright © 2009 Thilo Pionteck et al. T