a practical load-optimized vco design for low-jitter 5v 500 mhz digital phase-locked loop一个实际的装载优化vco设计low-jitter 5 v 500 mhz数字锁相环.pdfVIP

VLSI DESIGN (C) 2000 OPA (Overseas Publishers Association) N.V. 2000, Vol. 11, No. 2, pp. 107-113 Published by license under Reprints available directly from the publisher the Gordon and Breach Science Photocopying permitted by license only Publishers imprint. Printed in Malaysia. A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop* CHUA-CHIN WANG, YU-TSUN CHIEN and YING-PEI CHEN Dept. ofElectrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan 80424 (Received5 June 1999;In finalJbrm 1 October 1999) In high-speed digital systems and high-resolution display devices, the jitter effect of phase-locked loops (PLL)limits the system performance. Power supply noise coupling is one of the major causes of PLL jitter problems, especially with mixed-signal systems. The paper presents a targeted 5.0V 500MHz PLL which is implemented by a 0.6 um 1P3M digital CMOS technology. The features of the proposed design include a load- optimized 3-stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling current mirror. The jitter, thus, is reduced to 72.693 ps at 600MHz at the presence of supply noise, while the sensitivity is limited to 286.6 ps/V. This high-noise immunity design allows that the PLL can be integrated with dig