一种具有高线性度mos采样开关的采样保持电路-电子器件.pdfVIP

第36卷 第5期 电 子 器 件 Vol.36摇 No.5 2013年10 月 ChineseJournal of Electron Devices Oct.2013 A Sampling and Hold Circuit with High Linearity MOS Switch* WU Chubin,ZHANGZhang,YU Changhu,XIE Guangjun* (School of Electronic Science andApplied Physics,Hefei University of Technology,Hefei230009,China) Abstract:This paper presents a sample/ hold circuit,which includes a high linearity MOS switch.Through the op鄄 amp sharing used in the sample/ hold circuit,it can introduce afeedback voltage to the gate of the sampling switch during its sampling phase,and the feedback voltage can remarkably reduce the non鄄linearity introduced by on鄄 resistance of the sampling switch.Therefore it can achieve a high performance sample/ hold circuit.Based on SMIC 0.13 滋m standard CMOSprocess,the sample/ hold circuit isdesigned,and simulation results show that at sampling phase,the on鄄resistance of the sampling switch is only 0.2 赘 variation;and at the 80 Msample/ s sample rate, 30 MHz and 0.5V input signal,simulation results show that the spurious free dynamic range(SFDR)achieve pp 116 dB,which is about 34 dB over the conventional switch. Key words:sample/ hold circuit;sampling switch;op鄄amp sharing;nonlinearity EEACC:2570;1180摇 摇 摇 摇 doi:10.3969/j.issn.1005-9490.2013.05.016 一种具有高线性度MOS采样开关的采样保持电路* 吴楚彬,张摇 章,於昌虎,解光军* (合肥工业大学电子科学与与应用物理学院,合肥230009) 摘摇 要:提出了一种具有高线性度MOS采样开关的采样保持电路。 该电路通过运放的共享,在采样阶段对开关管的栅极引 入负反馈,有效地抑制开关导通电阻引入的非线性,实现了高性能的采样保持电路。 该电路采用SMIC0.13 滋m标准CMOS工 艺设计,仿真结果表明:在采样阶段,导通电阻大约只有0.2 赘 的变化;在采样时钟为80 MHz,输入信号为30 MHz、0.5V 时, pp 无杂散动态范围(SFDR)达到了116 dB,比传统自举开关的SFDR提高了34 dB。 关键词:采样保持电路;采样开关;运放复用;非线性 中图分类号:TN432摇 摇 摇 摇 文献标识码:A摇 摇 摇 摇 文章编号:1005-9490(2013)05-0651-05 摇 摇 随着CMOS集成电路工艺的迅速发展,尤其是