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single-stage vernier time-to-digital converter with sub-gate delay time resolution单级游标time-to-digital转换器与sub-gate延迟时间分辨率.pdfVIP

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single-stage vernier time-to-digital converter with sub-gate delay time resolution单级游标time-to-digital转换器与sub-gate延迟时间分辨率.pdf

    single-stage vernier time-to-digital converter with sub-gate delay time resolution单级游标time-to-digital转换器与sub-gate延迟时间分辨率

    Circuits and Systems, 2011, 2, 365-371 doi:10.4236/cs.2011.24050 Published Online October 2011 (/journal/cs) Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution Chin-Hsin Lin, Marek Syrzycki School of Engineering Science Simon Fraser University, Burnaby, Canada E-mail : cla 115@sfu.ca, marek@cs.sfu.ca Received June 1, 2011; revised June 22, 2011; accepted July 1, 2011

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