Synthesis and Scripting Techniques ... sunburst （合成和脚本技术u2026u2026）.pdfVIP

Expert Verilog, SystemVerilog Synthesis Training Synthesis and Scripting Techniques for Designing Multi- Asynchronous Clock Designs SNUG-2001 San Jose, CA Voted Best Paper 3rd Place Clifford E. Cummings, Sunburst Design, Inc. cliffc@ ABSTRACT Designing a pure, one-clock synchronous design is a luxury that few ASIC designers will ever know. Most of the ASICs that are ever designed are driven by multiple asynchronous clocks and require special data, control-signal and verification handling to insure the timely completion of a robust working design. 1.0 Introduction Most college courses teach engineering students prescribed techniques for designing completely synchronous (single clock) logic. In the real ASIC design world, there are very few single clock designs. This paper will detail some of the hardware design, timing analysis, synthesis and simulation methodologies to address multi-clock designs. This paper is not intended to provide exhaustive coverage of this topic, but is presented to share techniques learned from experience. 2.0 Metastability Quoting from Dally and Poultons book[6] concerning metastability: When sampling a changing data signal with a clock ... the order of the events determines the outcome. The smaller the time difference between the events, the longer it takes to determine which came first. When two events occur very close together, the decision process can take longer than the time allotted, and a synchronization failure