烧写内核的方法（Method for writing kernel）.docVIP

烧写内核的方法（Method for writing kernel） Embedded learning - class 12: burn, u-boot, kernel, and file system process (2011-02-19 17:53:33) reprinted label: register interrupt source, development board, file system transplantation, it classification: embedded learning Interrupted today, see S 3C2400.pdf, fourteenth chapter INTERRUPT CONTROLLER. Interrupt steps are divided into: 1, save the scene; 2, deal with the interruption; 3, restore the scene. Interrupts are divided into external interrupts and internal interrupts. The external interrupts are caused by pins of the CPU and IC (components), and the internal interrupts are generated by the internal controller of the CPU. The most basic interrupt registers are the PND register and the MASK register. The MASK register (MASK is not a register true name) each bit bit corresponds to a different interrupt source (a bit bit can correspond to a variety of interrupt sources) and sets whether or not it should ring off the source of the interrupt. The PND register (PND is not the real register name), each bit bit corresponds to different interrupt sources, and an interrupt source changes its corresponding bit bits. The interrupt diagram follows: Interrupt priority, see S3C2400.pdf fourteenth chapter INTERRUPT CONTROLLER P382 P363. Any CPU, PND register, bit position 1, indicates zero clearing. For related registers and concepts, see the S3C2400.pdf fourteenth chapter. Take your time. Set the basic steps of the interrupt: (to set the external interrupt of the K1 switch on the ARM board) 1, in the ARM board schematic to find K1 corresponding to the pin identified as EINT8, EINT8 corresponding to the CPU pin is identified as GPG0. The GPG0 is found in the manual, and the corresponding bit is set to 10 (EINT8). RGPGCON= rGPGCON (~ (30)) | (20); 2, in the manual to find EINT8 corresponding to the external interrupt controller for EXTINT1. REXTINT1= rEXTINT1 (~ (70)) | (20); / / EINT8 is decreased along the effective 3. Interrupt decla