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中断异常处理流程(Interrupt exception handling flow)
中断异常处理流程(Interrupt exception handling flow)
Computer architecture, exception or interrupt is a mechanism of emergency treatment system, almost all processors provide the mechanism. The main exception is a description from the perspective of processor passive angle, an abnormal operation caused by accident. The interrupt to the processor with active application means. But these two kinds of situations has certain similarities, is the request processor interrupt the normal program execution process, a mechanism into the specific program. If not specified, the abnormal and interrupt are not as strict distinction. In this paper after the actual verification code to the ARM9 interrupt handling process analysis, and designs the external interrupt handling procedures based on S3C2410 chip.
1. abnormal interrupt response and return
When the system runs, anomalies may occur at any time. When an exception appears after the ARM microprocessor performs the following steps:
1) the next instruction address into the corresponding link register LR, so that the program can start execution from the correct position in the treatment of abnormal return.
2) copy CPSR to the corresponding SPSR.
3) according to the type of abnormal, forced to set the running mode of CPSR bit.
4) force PC to fetch the next instruction from the exception vector address associated with the execution to jump to the corresponding exception handler at.
This is done by the ARM kernel, the user does not need to participate in the program. After the exception handling is completed, the ARM microprocessor will following operation from abnormal returns:
1) will connect the LR register value minus the offset corresponding to PC.
2) copy SPSR back to CPSR.
3) if in the exception handling set interrupt disable bit, to remove this.
The work must be implemented by the user in the interrupt handling function. In order to guarantee the ARM processor without exception occurs in an unknown state, in the design of the applica
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