Verilog数字频率计(00002).docVIP

摘 要 本文介绍了基于FPGA的数字频率计的设计方法，设计采用硬件描述语言Verilog ，在软件开发平台ISE上完成，可以在较高速时钟频率（48MHz）下正常工作。该数字频率计采用测频的方法，能准确的测量频率在10Hz到100MHz之间的信号。使用ModelSim仿真软件对Verilog程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan3A上取得良好测试效果。 关键词：FPGA，Verilog，ISE，测频方法 Abstract This paper introduces the design method of digital frequency meter based on FPGA, which use hardware description language-Verilog in software development platform ISE and can word in relatively high-speed clock of 48MHz. The frequency meter uses the method of frequency measurement, which could accurately measure the frequency of signals between 10Hz to 100MHz. This syste