第四章 VHDL速成2.pptVIP

第四章 VHDL速成2 1.VHDL语法结构 2.进程、函数、过程 下面两个实例分别描述了一个电平驱动的D触发器和一个脉冲驱动的D触发器。里面有单分支结构 区别一个信号在什么情况下是电平？什么情况下是脉冲？ 1.VHDL语法结构 （1）分支结构（单分支，多分支） （2）循环结构 多分支实例1： library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not_gate is Port ( a : in std_logic; b : out std_logic); end not_gate; architecture Behavioral of not_gate is begin -- b=not a; process(a) begin if a = 0 then b=1; else b=0; end if; end process; end Behavioral; 分支的嵌套 多分支实例2： library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a,b : in std_logic; c : out std_logic); end and2; architecture Behavioral of and2 is begin --c=a and b; process (a,b) variable tmp:std_logic_vector(1 downto 0); begin tmp:=ab; case tmp is when 00 = c=0; when 01 = c=0; when 10 = c=0; when 11 = c=1; when others = c=X; end case; end process; end Behavioral; 多分支实例3： architecture Behavioral of and2 is signal tmp:std_logic_vector(1 downto 0); begin tmp=ab; WITH tmp SELECT c= 0 WHEN 00, 0 WHEN 01, 0 WHEN 10, 1 WHEN 11, X WHEN OTHERS; end Behavioral; 多分支实例4： architecture Behavioral of and2 is signal tmp:std_logic_vector(1 downto 0); begin tmp=ab; c = 0 WHEN tmp = 00 ELSE 0 WHEN tmp = 01 ELSE 0 WHEN tmp = 10 ELSE 1 WHEN tmp = 11 ELSE X; end Behavioral; 循环结构实例：奇偶魈验码生成电路 函数,过程 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY func IS PORT ( a : IN STD_LOGIC_VECTOR (0 to 2 ) ; m : OUT STD_LOGIC_VECTOR (0 to 2 ) ); END ENTITY func ； ARCHITECTURE demo OF func IS FUNCTION sam(x ,y ,z : STD_LOGIC) RETURN STD_LOGIC IS BEGIN RETURN ( x AND y ) OR z ; END FUNCTION sam ； BEGIN PROCESS ( a ) BEGIN m(0) ?= sam( a(0), a(1), a(2) ) ; m(1) ?= sam( a(2), a(0), a(1) ) ;