东南大学soc课件10 芯片验证(3学时).pptVIP

SoC芯片验证 目录 Why Verification Verification Alternatives What is Design Verification? 设计验证verification的目的是确认设计的功能正确性和性能（速度和功耗等）满足设计要求，贯穿于设计的整个过程 Where are the Bugs? Functional specification system or behavior-level descriptions Design creation Inconsistent with spec RTL coding error (typo, X, logical error) Assumption on the environment Design/Physical implementation Synthesis tools Manual optimization Percentage of Total Flaws Importance of Verification More than half of all chips require one or more re-spins, and that functional errors were found in 74% of these re-spins. With increasing chip complexity, this situation could worsen. Who can afford that with = 1M Dollar NRE cost? Bug Fixing Cost in Time Cost of fixing a bug/problem increases as design progresses. Need verification method at early design stage Verification vs. Testing Agenda Why Verification Verification Alternatives Verification Alternatives Simulation FPGA Prototyping Formal Verification Verification Methodologies Software Simulation Dynamic verification method Bugs are found by running the design implementation. Thoroughness depends on the test vector used. Some parts are tested repeatedly while other parts are not even tested. Software Simulation Pros The design size is limited only by the computing resource. Simulation can be started as soon as the RTL description is finished. Set-up cost is minimal. Cons Slow (~k cycles/sec) ; Speed gap between the speed of software simulation and real silicon widens. (Simulation speed = size of the circuit simulated / speed of the simulation engine) The designer does not exactly know how much percentage of the design have been tested. RTL仿真 所使用的工具：VCS or Modelsim 仿真步骤： 搭建RTL验证环境 编写RTL的testbench 编写ARM的测试代码 把ARM测试代码的二进制文件加载到RTL验证环境中的RAM中 开始运行arm测试程序 观察仿真波形，观察调试信息 搭建RTL验证环境 以DMAC模块的验证为例 搭建RTL验证环境（续） SoC芯片 ARM7TDMI AMBA DMAC模块 SSI控制模块 EMI INTC SoC芯片外接模型 SSI外设模型 SRAM模型 SDRAM模型 NAND模型 编写RTL testbench 编写RTL testbench 在初始化部分添加 系统复位信号 系统时钟信号激励 把SoC芯片的各个管脚连接好