EDA技术实用教程(第二版)潘松黄继业第2版第8章_VHDL结构与要素.pptVIP

PORT ( clk : IN STD_LOGIC; Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC ); END; ARCHITECTURE one OF Speakera IS SIGNAL PreCLK, FullSpkS : STD_LOGIC; BEGIN DivideCLK : PROCESS(clk) VARIABLE Count4 : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PreCLK = 0; -- 将CLK进行16分频，PreCLK为CLK的16分频 IF Count411 THEN PreCLK = 1; Count4 := 0000; ELSIF clkEVENT AND clk = 1 THEN Count4 := Count4 + 1; END IF; 接下页 END PROCESS; GenSpkS : PROCESS(PreCLK, Tone)-- 11位可预置计数器 VARIABLE Count11 : STD_LOGIC_VEC