数字电子技术—VHDL语言.pptVIP

The basic thing to get out of this slide is that std_logic and std_logic_vector are what you should be using. More from Chapter 3 This was basically lifted from Chapter 1 of the book. VHSIC（Very High Speed Integrated Circuit）Hardware Description Language 翻译成中文就是超高速集成电路硬件描述语言 Logic Design With VHDL 补充内容：硬件描述语言 8.1 VHDL概述 V HSIC (Very High Speed Integrated Circuit-超高速集成电路) Hardware Description Language(硬件描述语言) VHDL is a Design Description Language(设计) VHDL is a Design Documentation Language (记录) VHDL is a Simulation Language (仿真) It is an IEEE Standard Language (国际标准) VHDL or HDL的优势 Very Fast Time-to-Market(高效性) Allows designers to quickly develop designs requiring tens of thousands of logic gates or more Provides powerful high-level constructs for describing complex logic Supports modular design methodology and multiple levels of hierarchy One language for design and simulation(功能强大丰富) Allows creation of device-independent designs that are portable to multiple PLD vendors(可移植性强) 8.2 VHDL 设计方式 VHDL设计称为实体，包括 ENTITY(实体)描述（可以简称实体） 和 ARCHITECTURE(结构体) ENTITY 描述了电路的 I/O接口情况 ARCHITECTURE 描述了具体功能的实现情况 8.2.1 实体描述（实体） A “BLACK BOX” The ENTITY describes the I/O of the black box (I/O端口描述) 例 8.1 Entity declaration ENTITY black_box IS PORT ( clk, rst: IN Bit; d: IN Bit_vector(7 DOWNTO 0); q: OUT Bit_vector(7 DOWNTO 0); co: OUT Bit); END black_box; PORTS have an associated(属性): name(名字), mode(模式), and type(类型) 实体名，一般要和设计文件同名 IEEE-1164版本(相对于IEEE-1076版本) A package created to solve the limitations of the BIT type Nine values instead of just two (0 and 1) STD_LOGIC and STD_LOGIC_VECTOR are now the industry standard logic type for digital design STD_LOGIC and STD_LOGIC_VECTOR are used instead of BIT and BIT_VECTOR when a multi-valued logic system is required STD_LOGIC and STD_LOGIC _VECTOR must be used when tri-state logic (Z) is required To be able to use this new type, you need to add 2 lines to your code: LIBRARY ieee; USE ieee.std_lo