数字系统设计-控制器与Rom.ppt

* ZDMC What Complementary about CMOS? Complementary devices work in pairs n-channelopen when voltage at G is lowcloses when: voltage(G) voltage (S) + ? p-channelclosed when voltage at G is lowopens when: voltage(G) voltage (S) – ? G S D G S D * ZDMC HW 补充讲义 1，2 数字系统设计 * 数字系统设计 * Diagram of a 32 x 4 memory; Virtual arrangement of memory cells into 32 four-bit words. 数字系统设计 * The classical SRAM cell looks like this. It consists of two back-to-back inverters that serves as a flip-flop. Here is an expanded view of this cell, you can see it consists of 6 transistors. In order to write a value into this cell, you need to drive from both sides. For example, if you want to write a 1, you will drive “bit” to 1 while at the same time, drive “bit bar” to zero. Once the bit lines are driven to their desired values, you will turn on these two transistors by setting the word line to high so the values on the bit lines will be written into the cell. Remember now these are very very tiny transistors so we cannot rely on them to drive these long bit lines effectively during read. Also, the pull down devices are usually much stronger than the pull up devices. So the first thing we need to do on read is to charge these two bit lines to a high values. Once these bit lines are charged to high, we will turn on these two transistors so one of these inverters (the lower one in our example) will start pulling one of the bit line low while the other bit line will remain at HI. It will take this small inverter a long time to drive this long bit line to low but we don’t have to wait that long since all we need to detect the difference between these two bit lines. And if you ask any circuit designer, they will tell you it is much easier to detect a “differential signal” (point to bit and bit bar) than to detect an absolute signal. +2 = 30 min. (Y:10) 数字系统设计 * 数字系统设计 * 数字系统设计 * 数字系统设计 * 数字系统设计 * 数字系统设计 ZDMC * ZDMC ROM Structure Similar to a PLA structure but with a fully decoded AND a