实验四 译码器.docx

实验名称：组合逻辑VHDL设计----译码器班级：09通信1学号 姓名：顾礼萍一、用WITH-SELECT语句实现2-4译码器 1.实体框图 2.程序设计LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECODER24B IS PORT(A1,A0:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END ENTITY DECODER24B;ARCHITECTURE ONE OF DECODER24B ISSIGNAL S: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN S=A1A0; WITH S SELECT Y=1110 WHEN00, 1101 WHEN01, 1011 WHEN10, 0111 WHEN11, ZZZZ WHEN OTHERS;END ARCHITECTURE ONE;3.仿真波形图 4.仿真波形分析二、用WITH-SELECT语句实现带使能端的3-8译码器1.实体框图2.程序设计LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECODER38B IS PORT(A2,A1,A0:IN STD_LOGIC; S3,S2,S1:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END ENTITY DECODER38B;ARCHITECTURE ONE OF DECODER38B ISSIGNAL G: STD_LOGIC_VECTOR(4DOWNTO 0); BEGIN G=S1(S2 AND S3)A2A1A0; WITH G SELECT YWHEN10000,WHEN10001,WHEN10010,WHEN10011,WHEN10100,WHEN10101,WHEN10110, WHEN10111, ZZZZZZZZ WHEN OTHERS;END ARCHITECTURE ONE;3.仿真波形图4.仿真波形分析三、用WITH-SELECT语句实现驱动共阳极数码管七段显示译码器1.实体框图2.程序设计LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECODER7B IS PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)END ENTITY DECODER7B;ARCHITECTURE ONE OF DECODER7B ISSIGNAL S: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN S=A3A2A1A0; WITH S SELECT Y=1111111 WHEN0000, 1111001 WHEN0001, 0100100 WHEN0010, 0110000 WHEN0011, 0011001 WHEN0100, 0010010 WHEN0101, 0000010 WHEN0110, 1111000 WHEN0111, 0000000 WHEN1000, 0010000 WHEN1001, ZZZZZZZ WHEN OTHERS;END ARCHITECTURE ONE;3.仿真波形图4.仿真波形分析思考题设计共阴极七段显示译码器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DECODER7B IS PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)END ENTITY DECODER7B;ARCHITECTURE ONE OF DECODER7B ISSIGNAL S: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN S=A3A2A1A0; WITH S SELECT Y=0000000 WHEN0000, 0000110 WHEN0001, 1011011 WHEN0010, 1001111 WHEN0011, 1100110 WHEN0100, 1101101 WHEN0101, 1111101 WHEN0110, 0000111 WHEN0111, 1111111 WHEN1000, 1101111 WHEN10