ch8part2PPT课件.pptVIP

8.10 memory control signals Minimum mode Control signals produced by the processor itself Maximum mode Control signals produced by 8288 Minimum mode memory control signals 8088 IO/M DT/R RD WR DEN SSO 8086 M/IO No SSO BHE Maximum modememory control signals Different signals Produced by 8288 8.11 read write bus cycles Time sequence of bus operation Read cycle for 8088 4 phases T1 T2 T3 T4 T1 address out, latched by ALE, IO/M DT/R SSO out T2 S3-S6 out AD0-AD7 High-Z RD DEN switched to 0 T3 data out T4 data still keeping, RD latch, DEN return to inactive Read cycle for 8086 BHE o