AnDROID程序开发例题截图.docxVIP

控存编程校验主存编程校验复杂模型机运行中断运行综合报告Release 13.4 - xst O.87xd (nt)Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.-- Parameter TMPDIR set to xst/projnav.tmpTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.13 secs-- Parameter xsthdpdir set to xstTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.13 secs-- Reading design: RAM0.prjTABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : RAM0.prjIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : RAM0Output Format : NGCTarget Device : xc6slx45-2-fgg484---- Source OptionsTop Module Name : RAM0Automatic FSM Extraction : YESFSM Encoding Algorithm : AutoSafe Implementation : NoFSM Style : LUTRAM Extraction : YesRAM Style : AutoROM Extraction : YesShift Register Extraction : YESROM Style : AutoResource Sharing : YESAsynchronous To Synchronous : NOShift Registe