以太网知识-RMII and SMII接口.doc

以太网知识(2)-RMII / SMII接口 作者:luqiliang 日期:2010-5-4 13:47:22 字体大小: 小 中 大 本文主要分析MII/RMII/SMII，以及GMII/RGMII/SGMII接口的信号定义，及相关知识，同时本文也对RJ-45接口进行了总结，分析了在10/100模式下和1000M模式下的连接方法。 ? 续--上篇文章“以太网知识(1)-MII接口” 1.5 Electrical Character MII接口的电气特性可以分为Driver characteristics和Receiver characteristics。 针对于Driver characteristics的DC电气特性而言，Spec要求所有MII接口The high (one) logic level output potential Voh shall be no less than 2.40 V at an output current Ioh of –4.0 mA. The low (zero) logic level output potential Vol shall not be greater than 0.40 V at an output current IoLof 4.0 mA。这个就是LVTTL常用的逻辑标准。 针对于Driver characteristics的AC电气特性而言，Drivers must also meet certain ac specifications in order to ensure adequate signal quality for electrically long point-to-point transmission paths. The ac specifications shall guarantee the following performance requirements. The initial incident potential change arriving at the receiving end of a point-to-point MII signal path plus its reflection from the receiving end of the path must switch the receiver input potential monotonically from a valid high (one) level to Vil ≤ Vil(max)–200 mV, or from a valid low (zero) level to Vih ≥ Vih(min) + 200 mV. Subsequent incident potential changes arriving at the receiving end of a point-to-point MII signal path plus their reflections from the receiving end of the path must not cause the receiver input potential to reenter the range Vil(max) – 200 mV Vi Vih(min) + 200 mV except when switching from one valid logic level to the other. Such subsequent incident potential changes result from a mismatch between the characteristic impedance of the signal path and the driver output impedance。 ? 2．RMII接口分析 ? 2.1 RMII接口信号定义 RMII接口（Reduced MII接口）是简化的MII接口。它也分为MAC模式和PHY模式。 RMII接口接收、发送和控制的同步参考时钟REF_CLK是由外部时钟源提供的50MHz信号。这与原来的MII接口不同，MII接口中发送和接收的时钟是分开的，且都是由物理层芯片提供给MAC层芯片。 这里需要注意的是由于数据接收时钟是由外部晶振提供而不是由载波信号提取的，所以在物理层芯片内的数据接收部分要设计一个FIFO，用来协调两个不同的时钟，在发送接收的数据时提供缓冲。物理层芯片的发送部分则不需要一个FIFO，它直接将接收到的数据发送出去就可以了。 CRS_DV是MII中的RXDV 和CRS(Carrier_Se