毕FPGA信号发生器业设计外文翻译.doc

FPGA-based signal processing for the LHCb silicon strip detectors G. Haefeli, A. Bay and A. Gong Abstract We have developed an electronic board (TELL1) to interface the DAQ system of the LHCb experiment at CERN. Two hundred and eighty-nine TELL1 boards are needed to read out the different subdetectors including the silicon VEertex LOcator (VELO) (172?k strips), the Trigger Tracker (TT) (147?k strips) and the Inner Tracker (129?k strips). Each board can handle either 64 analog or 24 digital optical links. The TELL1 mother board provides common mode correction, zero suppression, data formatting, and a large network interface buffer. To satisfy the different requirements we have adopted a flexible FPGA design and made use of mezzanine cards. Mezzanines are used for data input from digital optical and analog copper links as well as for the Gigabit Ethernet interface to DAQ. Keywords: LHCb; DAQ; FPGA; Gigabit Ethernet; Silicon strip detectors; Common mode; Zero suppression 1. Introduction The LHCb [1] experiment at CERNs Large Hadron Collider (LHC) is dedicated to the studies of CP violation and rare decays in the “beauty” sector. For the DAQ interface an LHCb common readout board (TELL1) has been developed allowing to implement event synchronization, pedestal subtraction, Common Mode (CM) noise filtering, clusterization and network interfacing. In the following we give an overview of the LHCb DAQ architecture, a description of the TELL1 processor board and discuss the processing required for the LHCb silicon vertex detector (VELO) and by the silicon tracker detectors (TT and IT). LHCb has three levels of DAQ electronics, corresponding to the three levels of trigger called L0, L1 and High-Level Trigger (HLT). The L0 electronics is placed close to the detector and requires radiation-hard or radiation-tolerant components. To minimize the amount of electronics prone to the radiation effects, the L1 electronics is placed behind a shielding wall, quite far from the interacti