A Guide for On Chip Inductor Design in a Convetional CMOS Process for RF Applications英文电子书.pdf

A Guide for On-Chip Inductor Design in a Conventional CMOS Process for RF Applications By Jaime Aguilera and Joaquín de Nó, Universidad de Navarra; Andrés García-Alonso, CEIT; Frank Oehler, Heiko Hein and Josef Sauerer, Fraunhofer Institut für Integrierte Schaltungen his article gives a simple set of rules for grated inductor by using nonstandard options in the design of integrated inductors with a silicon technologies have been proposed: use of Tgood quality factor in a standard CMOS porous silicon layers over silicon substrate [2], process. This guide takes into account almost all or etching the silicon substrate under the induc- the degrees of freedom that a designer has when tor [3]. Other designers have introduced ways to creating an inductor: the number of sides, the improve the performance of an inductor in a number of metal layers, the center hole, the standard silicon technology with no extra cost, external radius, metal width and spacing. To for example, a patterned ground shield [4] or a verify these rules, a set of inductors for different bias n-well beneath the inductor [5, 6]. This applications were patterned and measured and article introduces the rules for the design the quality factors (Q) between 4.6 and 6 were geometry of the spiral. These rules help design- obtained. ers to design integrated inductors with good Q A