一种分片式多核处理器的用户级模拟器-软件学报.pdfVIP

ISSN 1000-9825, CODEN RUXUEW E-mail: jos@ Journal of Software, Vol.19, No.4, April 2008, pp.1069− 1080 DOI: 10.3724/SP.J.1001.2008.01069 Tel/Fax : +86-10 © 2008 by Journal of Software. All rights reserved. ∗ 一种分片式多核处理器的用户级模拟器 1,2+ 3 1,2 1 1 黄 琨 , 马 可 , 曾洪博 , 张 戈 , 章隆兵 1( 中国科学院 计算技术研究所 系统结构重点实验室,北京 100080) 2 ( 中国科学院 研究生院,北京 100049) 3( 中国科学技术大学 计算机科学与技术系,安徽 合肥 230027) A Use-Level Simulator for Tiled Chip Multiprocessor 1,2+ 3 1,2 1 1 HUANG Kun , MA Ke , ZENG Hong-Bo , ZHANG Ge , ZHANG Long-Bing 1(Key Laboratory of Computer System and Architecture, Institute of Computing Technology, The Chinese Academy of Sciences, Beijing 100080, China) 2 (Graduate University, The Chinese Academy of Sciences, Beijing 100049, China) 3(Department of Computer Science and Technology, University of Science and Technology of China, Hefei 230027, China) + Corresponding author: Phn: +86-10 E-mail: huangkun@ Huang K, Ma K, Zeng HB, Zhang G, Zhang LB. A use-level simulator for tiled chip multiprocessor. Journal of Software, 2008,19(4):1069−1080. /1000-9825/19/1069.htm Abstract: As the transistor resources and delay of interconnect wires increase, the tiled multi-core processor has been a new direction for multi-core processor. In order to thoroughly study new type processor and explore the design space of it, this paper designs and implements a user-level performance simulator f