VerilogHDL举例5.docVIP

4 位数字频率计 4 位数字频率计（控制模块，输入1Hz时钟信号） module fre_ctrl(clk,rst,count_en,count_clr,load); output count_en,count_clr,load; input clk,rst; reg count_en,load; always @(posedge clk) begin if(rst) begin count_en=0; load=1; end else begin count_en=~count_en; load=~count_en; end end assign count_clr=~clkload; endmodule 4 位数字频率计（计数模块） module count10(out,cout,en,clr,clk); output[3:0] out; output cout; input en,clr,clk; reg[3:0] out; reg cout; always @(posedge clk or posedge clr) begin if (clr) begin out = 0; cout = 0; end else if(en) begin if(out==9) begin out=0; cout = 1; end else begin out = out+1; cout = 0; end end end endmodule 4 位数字频率计（锁存器模块） module latch_16(qo,din,load); output[15:0] qo; input[15:0] din; input load; reg[15:0] qo; always @(posedge load) begin qo=din; end endmodule 4 位数字频率计（顶层模块） 交通灯控制器 module traffic(CLK,EN,LAMPA,LAMPB,ACOUNT,BCOUNT); output[7:0] ACOUNT; //A方向灯的时间显示 output[7:0] BCOUNT; //B方向灯的时间显示 output[3:0] LAMPA; //控制A方向4盏灯的亮灭，分别对应红、黄、绿、左拐 output[3:0] LAMPB; //控制B方向4盏灯的亮灭 input CLK,EN; reg[7:0] numa,numb; reg tempa,tempb; reg[2:0] counta,countb; reg[7:0] ared,ayellow,agreen,aleft,bred,byellow,bgreen,bleft; reg[3:0] LAMPA,LAMPB; always @(EN) if(!EN) begin ared =8h55; ayellow =8h5; agreen =8h40; aleft =8h15; bred =8h65; byellow =8h5; bleft =8h15; bgreen =8h30; end assign ACOUNT=numa; assign BCOUNT=numb; always @(posedge CLK) begin if(EN) begin if(!tempa) begin tempa=1; case(counta) 0: begin numa=agreen; LAMPA=2; counta=1; end 1: begin numa=ayellow; LAMPA=4; counta=2; end 2: begin numa=aleft; LAMPA=1; counta=3; end 3: begin numa=ayellow; LAMPA=4; counta=4; end 4: begin numa=ared; LAMPA=8; counta=0; end default: LAMPA=8; endcase end else begin if(numa1) if(numa[3:0]==0) begin numa[3:0]=4b1001; numa[7:4]=numa[7:4]-1; end else numa[3:0]=numa[3:0]-1; if (numa==2) tempa=0; end end else begin LAMPA=4b1000; counta=0; tempa=0; end