VerilogHDL简单电路设计 有限状态机电路设计实例.pptVIP

有限状态机电路设计实例 “10010”序列检测分析 “10010”序列检测电路设计 “10010”序列检测电路测试 交通灯电路 交通灯电路（一） module Trafic_Lamp(clk,rst,green,yellow,red); input clk,rst; output green,yellow,red; parameter [1:0] init = 0, g = 1, y = 2, r = 3; reg green,yellow,red; reg [1:0]fsm; reg [4:0]count; always @(posedge clk or negedge rst) begin if(!rst) begin fsm = 0;count = 0; end else begin ???? end end endmodule 交通灯电路（一） casex(fsm) init: begin fsm = g;count = 0;end g : begin red = 0; green = 1; yellow = 0; if(count==25-1)begin fsm = y;count=0;end else count = count+1; end y : begin red = 0; green = 0; yellow = 1; if(count==2-1)begin fsm = r;count=0;end else count = count+1; end r : begin red = 1; green = 0; yellow = 0; if(count==15-1)begin fsm = g; count = 0;end else count = count+1; end default : begin red = 0; green = 0; yellow = 0; end endcase 交通灯电路（二） 交通灯电路（二） * * 00100101011011001 00100100101101101 11100100101101101 11100101011011001 module seqdet(x,z,clk,rst); input x,clk, rst; output z; reg [2:0] state; wire z; parameter IDLE = 3 d0, A = 3 d1, B = 3 d2, C = 3 d3, D = 3 d4, E = 3 d5, F = 3 d6, G = 3 d7; assign z = (state==D x==0)? 1:0; always @(posedge clk or negedge rst) if(!rst) state=IDLE; else begin ???? end endmodule casex( state) IDLE: if (x==1) state = A; else state = IDLE; A: if (x==0) state = B; else state = A; B: if (x==0) state = C; else state = F; C: if (x==1) state = D; else state = G; D: if (x==0) state = E; else state = A; E: if (x==0) state = C; else state = A; F: if (x==1) state = A; else state = B; G: if (x==1) state = F; else state = B; default: state = IDLE; endcase `timescale 1ns/1ns module seqdet_tb; reg clk, rst; reg [23:0