基于FPGA技术实现智能抢答器的设计论文.docVIP

河北工业大学城市学院 毕业设计说明书 作 者： 陈厚黎 学 号： 系： 信息工程系 专业： 电子科学与技术 题 目： 基于FPGA技术实现智能抢答器的设计 指导者： 伍萍辉 教授 (姓 名) (专业技术职务) 评阅者： (姓 名) (专业技术职务) 年 月 日 毕业设计（论文）中文摘要 基于FPGA技术实现智能抢答器的设计 摘要： 智力抢答器作为一种电子产品，很早就广泛应用于各种智力和知识竞赛场合。但之前所使用的抢答器有的电路复杂不便于制作，可靠性低，实现起来非常困难。FPGA 的出现从根本上改变了以往数字电路的设计模式，使电路由硬件设计转变为软件设计。从而提高了设计的灵活性，降低了电路的复杂程度，功能升级方便，大大缩短了设计周期，减少了研发经费。本设计采用FPGA现场可编程技术,避免了硬件电路的焊接与调试,同时由于FPGA的I/O端口丰富,可以在设计的基础上略加修改实现具有多组输入的抢答器,增强了系统的灵活性。本系统具有较好的稳定性和可靠性，能准确、公正、直观地判断出第一抢答者，并通过抢答器的指示灯显示和蜂鸣器等手段指示出第一抢答者。 关键字： 智力抢答器 FPGA 缩短周期 稳定性 可靠性 毕业设计（论文）外文摘要 Title The design of the intelligent vies to answer first device based on FPGA technology Abstra Intelligence responder as a kind of electronic products, are widely used in all kinds of intelligence and knowledge competition very early.But before the buzzer used some circuit is not easy to make, low reliability, is very difficult to implement.The appearance of FPGA fundamentally changed the previous digital circuit design pattern, make the circuit designed by hardware into software design.So as to improve the flexibility of the design, reduces the complexity of the circuit, upgrade convenient, greatly shorten the design cycle, reduce the research and development spending.This design USES FPGA field programmable technology, avoid the welding and debugging of hardware circuit, at the same time because the I/O port of the FPGA is rich, can be realized on the basis of the design a little modification has multiple sets of input buzzer, enhance the flexibility of the system.This system has good stability and reliability, accurate, fair and visually determine the first vies to answer first, and through the responder light display and buzzer show first vies to answer fir