基于FPGA的数字跑表功能的数字钟设计论文.docVIP

南京大学 毕 业 论 文（设 计） 作 者: 学 号： 系 部: 专 业: 电子信息科学与技术 （方 向）: 题 目: 多功能数字钟 指导老师 王怀登 讲师/硕士 提交日期 2014年5月12日 摘 要 近年来，科学技术发展飞速，人们的生活质量也不断提高。传统的时钟已经无法满足现代人的生活要求。多功能数字钟无论在形态还是在性能上都改变了原有的风格。 本次设计基于原始的数字钟，在此基础上增加了诸项功能。不仅具备时，分，秒计数功能，另外增加了校时功能，整点报时功能，闹钟功能以及数字跑表功能。设计中采用了EDA技术，使用硬件描述语言Verilog HDL对各大功能模块的逻辑功能进行代码编写。于QuartusII软件环境下，采用层次化设计与模块化设计的方法，由各个功能模块连接建立顶层图，构成基于FPGA的多功能数字钟。 设计实验板的主芯片为EP3C25Q240C8，多功能数字钟由分频器模块，时钟计数模块，校时控制模块，闹钟模块，整点报时与音乐演奏模块，数据选择模块，译码显示模块，按键去抖动模块和数字跑表模块构成。经过程序编译和模块仿真，在实验板上下载验证，该系统可以完成时，分，秒的正常显示，通过按键切换功能模式，进入闹钟时间设定，校时，数字跑表模式。可以手动调整时间，设定闹钟及数字跑表计时。 关键词：FPGA； Verilog HDL； 数字钟； THE DIGITAL CLOCK WITH STOPWATCH FUCTION ABSTRACT In recent years, the rapid development of science technology, quality of life is also rising. Traditional clock has been unable to meet the requirements of modern life. Both in the form of multi-function digital clock or in the performance has changed the original style. The design is based on the original digital clock, on the basis of it increased various functions. Not only have the time, minutes, seconds count function, also add the function of adjusting time, the whole point timekeeping function, alarm function and digital stopwatch functions. EDA technology used in the design, using Verilog HDL hardware description language for logic functions in major functional modules of code to write. Under Quartus II software environment, using hierarchical design methods and modular design, the top chart established by the various functional modules connecting each other, constitute FPGA-based multifunctional digital clock. The main system chip of design experiment board is EP3C25Q240C8, multifunctional digital clock is composed of the divider module, the clock counting module, the adjust time control module, the alarm module, the whole point timekeeping and music module, the data selection module, the decoding module, the key to jitter module and digital stopwatch module. After the program compiled and module simulation, downloa