[信息与通信]第5章 VHDL设计进阶.pptVIP

3.CASE语句 5.2.3 带有并行置位的移位寄存器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SHFRT IS -- 8位右移寄存器 PORT ( CLK，LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB : OUT STD_LOGIC ); END SHFRT; ARCHITECTURE behav OF SHFRT IS BEGIN PROCESS (CLK, LOAD) VARIABLE REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN IF CLKEVENT AND CLK = 1 THEN IF LOAD = 1 THEN -- 装载新数据 REG8 := DIN; ELSE REG8(6 DOWNTO 0) := REG8(7 DOWNTO 1); END IF;