Boxcar FIR Filter：Boxcar滤波器.ppt

Boxcar FIR Filter Shadi Hawawini Pearl Yuan Amr Darwish Karun Malhotra Advisor: Dr. Parent May 8, 2006 Agenda Abstract Introduction Why Simple Theory Background Information Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions Abstract We designed a 4-bit Finite Impulse Response (FIR) Filter that operates at 200 MHz Impulse Response - A set of FIR coefficients, which represent all possible frequencies. Tap - A coefficient/delay pair. The number of FIR taps is an indication of the amount of memory required to implement the filter. Introduction One of the most fundamental elements for a DSP system is an FIR Filter. There is no feedback, which results in a finite output value of zero. The filter is mathematically expressed using the following difference equation: FIR Block Diagram Longest Path Calculations Schematic Layout Successful DRC check Successful Extraction Report Successful LVS Report Successful LVS Report cont. Simulations Simulation Simulation Post Extraction Post Extraction cont. Propagation Delay Waveform Propagation Delay Cost Analysis Estimated time spent on each phase of the project: Verifying Logic = 2 weeks Verifying Timing = N/A Layout = 15 hours Post Extracted Timing = 5 hours Lessons Learned A project of this nature requires ample time to complete it, before its deadline. Verify logic of individual components. Extra care needed when designing the layout. Summary Acknowledgements Dr. Parent, for teaching us not to overcomplicate our designs. * The FIR Filter consist of three main components: 1) A D Flip-Flop to implement a simple delay. 2) A Multiplier to implement the coefficients, which in our case we are using a Boxcar filter, meaning all coefficients are 1. 3) A Full adder to sum the nodes at the end of each Tap. Simulations Because FIR Filters are such an important element of DSP design, it was beneficial to do a project like this to strengthen understanding of the concept A low cost, easy to impleme