EDA基于VHDL的电子密码锁设计报告.doc

密码锁设计 密码锁设计顶层电路图 （2）顶层时序仿真 分频模块 （1）10分频程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yourname_div10 is port(clk:in std_logic; co:out std_logic); end ; architecture behav of yourname_div10 is signal count:std_logic_vector(3 downto 0); begin process(clk) begin if clkevent and clk=1then if count=1001then count=0000; co=1; else count=count+1; co=0; end if; end if; end process; end behav; （2）5分频程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yourname_div5 is port(clk:in std_logic; co:out std_logic); end; architecture behav of yourname_div5 is signal count:std_logic_vector(2 downto 0); begin process(clk) begin if clkevent and clk=1then if count=100then count=000; co=1; else count=count+1; co=0; end if; end if; end process; end behav; （3）10分频时序仿真波形 （4）5分频时序仿真波形 从以上波形仿真可以看出该板块10分频模块的输出是输入信号的10分频，同理5分频的输出是输入信号的5分频。  附录三：消抖模块 （1）消抖模块程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yourname_xiaodou is port(clk_1k:in std_logic; keyin:in std_logic; keyout:out std_logic); end ; architecture behav of yourname_xiaodou is signal n:integer range 0 to 29; begin process(clk_1k) begin if keyin=1 then n=0; keyout=1; elsif clk_1kevent and clk_1k=1 then if n29 then n=n+1; keyout=1; else n=29; keyout=0; end if; end if; end process; end behav; （2）仿真波形 附录四：输入模块 （1）输入模块程序 1.yourname_count10模块程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yourname_count10 is port(clk:in std_logic; bcd:buffer std_logic_vector(3 downto 0)); end ; architecture behav of yourname_count10 is begin process(clk) begin if clkevent and clk=1 then if bcd=1001then bcd=0000; else bcd=bcd+1;