fpga常用程序例子.docVIP

1. 或门的描述 LIBRARY IEEE; USE IEEE.STD LOGIC 1164.ALL ENTITY or1 IS PORT( a,b: IN STD_LOGIC; y: OUT STD LOGIC); END or1; ARCHITECTURE example1 OF or1 IS BEGIN y=a OR b; END example1; 2. 半加器的描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_adder IS PORT(a,b:IN STD_LOGIC; so,co:OUT STD_LOGIC); END h_adder; ARCHITECTURE example2 OF h_adder IS BEGIN so=a XOR b; co=a AND b; END example2; 3. 2选1数据选择器的描述 LIBRARY IEEE； USE IEEE.STD LOGIC 1164.ALL ENTITY mux21 IS PORT( a,b: IN STD LOGIC; s: IN STD LOGIC; y: OUT STD LOGIC); END mux21; ARCHITECTURE example3 OF mux21 IS B