【精选】SN74LVC2G00WDCTREP, 规格书,Datasheet 资料.pdfVIP

【精选】SN74LVC2G00WDCTREP, 规格书,Datasheet 资料.pdf

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【精选】SN74LVC2G00WDCTREP, 规格书,Datasheet 资料

SN74LVC2G00W-EP DUAL 2-INPUT POSITIVE-NAND GATE SCES645 – SEPTEMBER 2005 FEATURES • Controlled Baseline • ±24-mA Output Drive at 3.3 V – One Assembly/Test Site, One Fabrication • Typical VOLP (Output Ground Bounce) Site 0.8 V at V = 3.3 V, T = 25°C CC A • Extended Temperature Performance of –55°C • Typical VOHV (Output VOH Undershoot) to 115°C 2 V at V = 3.3 V, T = 25°C CC A • Enhanced Diminishing Manufacturing • Ioff Supports Partial-Power-Down Mode Sources (DMS) Support Operation • Enhanced Product-Change Notification • Latch-Up Performance Exceeds 100 mA Per • Qualification Pedigree (1) JESD 78, Class II • Supports 5-V V Operation • ESD Protection Exceeds JESD 22 CC • Inputs Accept Voltages to 5.5 V – 2000-V Human-Body Model (A114-A) • Max t of 5.3 ns at 3.3 V – 1000-V Charged-Device Model (C101)

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