EDA(第四章)4.3.pptVIP

8位奇校验电路仿真结果： 例：用while…loop语句描述的8位奇偶校验电路 ENTITY mux IS PORT (d0,d1,sel : IN BIT; q : OUT BIT ); END mux; ? ARCHITECTURE one OF mux IS BEGIN cale:PROCESS(d0,d1,sel) VARIABLE temp1,temp2,temp3: BIT; BEGIN temp1:=d0 AND sel; temp2:=d1 AND (NOT sel); temp3:=temp1 OR temp2; q = temp3; END PROCESS; END one ; ENTITY mux IS PORT (d0,d1,sel : IN BIT; q : OUT BIT ); END mux; ARCHITECTURE connect OF mux IS SIGANL temp1,temp2,temp3:BIT; BEGIN cale: BLOCK BEGIN