VHDL抢答器的设计毕业设计论文.doc

摘 要 当今的社会竞争日益激烈，选拔人才，评选优胜，知识竞赛之类的活动愈加频繁，那么也就必然离不开抢答器。抢答器是在竞赛、文体娱乐活动（抢答活动）中，能准确、公正、直观地判断出抢答者的机器。 本次设计的抢答器主要是尝试采用基于EDA技术的方法设计一种竞赛抢答器。整个设计包括抢答鉴别单元，定时单元，计分单元，译码器及VHDL语言和FPGA/CPLD设计的数字抢答器。本设计就采用了VHDL语言在Quartus II环境下来完成系统的设计文件，对模块的程序进行输入，编译，综合，适配，并将抢答器设置成硬件符号入库，最后各个部分元件符号链接到一起得到顶层模块，顶层模块同时也可用VHDL语言描述，实现控制器的功能要求。最后通过仿真观察其功能。 关键词：抢答器，EDA技术，VHDL语言，模块 Abstract Todays increasingly fierce social competition, talent selection, selection of winning, knowledge contests activities more frequent, such as then will must be inseparable from the buzzer. Responder is in the contest, style entertainment (vies to answer first activities), accurate, fair and visually determine vies to answer first the machine. The responder is primarily designed to try the method based on EDA technology to design a competition responder. Whole design including vies to answer first differential unit, the timing unit, the unit of scoring, the decoder and the FPGA/CPLD and VHDL language design of digital vies to answer first device. This design USES the VHDL language in the Quartus II environment down to complete the system design documents, the application of module input, compilation, comprehensive, adaptation, and the buzzer is set to hardware symbol library, and finally the parts components symbolic links to get the top-level module, along the top module at the same time also can be used VHDL language description, realize the functions of the controller. Finally through the simulation to observe its function. Key Words: Responder, EDA technology, VHDL language, modules 目 录 1 引言 1 2 方案设计与论证 1 2.1抢答器系统设计要求 1 2.2方案论证与选择 2 2.2.1方案一 2 2.2.2方案二 2 2.2.3方案的选择 3 2.3系统总体设计思想 3 3 单元模块电路的设计和实现 4 3.1抢答鉴别模块的设计实现 4 3.1.1设计原理 4 3.1.2功能仿真 5 3.2计时模块的设计与实现 6 3.2.1设计原理 6 3.2.2计时模块的仿真 6 3.3 译码显示模块的设计与实现 7 3.3.1设计原理 7 3.3.2 功能仿真 7 3.4 报警模块的设计与实现 7 3.4.1设计原理 7 3.4.2 功能仿真 8 3.5 抢答器系统的设计与实现 8 3.5.1 总体设计原理 8 3.5.2 功能仿真 9 4 总结 10 参考文献 12 致 谢 13 1 引言 当今的社会竞争日益激烈，选拔人才，评选优