DE2实验练习解答—lab6Adders.docVIP

 HYPERLINK /halflife/archive/2010/07/05/1771746.html /halflife/archive/2010/07/05/1771746.html 本练习的目的是实现算术运算电路。每种电路用2种方法实现：Verilog语言描述和LPM。并比较其不同。 Part I 8-bit的加法器 要求： 支持有符号的数的2的补码的形式； 带溢出信号，当结果不对时，溢出为1； 代码part1.v 1 /* 2 *(C) yf.x 2010  3 * 4 *Complier :Quartus II 9.1 5 *Filename :adder_8b_reg.v 6 *Description:A 8-bit adder,top-level file.which support signed number in 2s complement. 7 *Release :06/30/2010 1.0 8 */ 9  10 module adder_8b_reg(SW, //加数A和B 11 KEY, //脉冲和复位 12 LEDR, //和 13 LEDG, //溢出 14 HEX7, //16进制显示加数A 15 HEX6, 16 HEX5, //16进制显示加数B 17 HEX4, 18 HEX1, //16进制显示和 19 HEX0 20 ); 21  22 input [15:0]SW; 23 input [1:0]KEY; 24 output [7:0]LEDR; 25 output [8:8]LEDG; 26 output [6:0]HEX7,HEX6,HEX5,HEX4,HEX1,HEX0; 27  28 adder u0(.A(SW[15:8]), 29 .B(SW[7:0]), 30 .clk(KEY[1]), 31 .rst_n(KEY[0]), 32 .sum(LEDR), 33 .overflow(LEDG) 34 ); 35  36 seg7_lut u1(.oseg(HEX7), 37 .idig(SW[15:12]) 38 ); 39 seg7_lut u2(.oseg(HEX6), 40 .idig(SW[11:8]) 41 ); 42 seg7_lut u3(.oseg(HEX5), 43 .idig(SW[7:4]) 44 ); 45 seg7_lut u4(.oseg(HEX4), 46 .idig(SW[3:0]) 47 ); 48 seg7_lut u5(.oseg(HEX1), 49 .idig(LEDR[7:4]) 50 ); 51 seg7_lut u6(.oseg(HEX0), 52 .idig(LEDR[3:0]) 53 ); 54  55 endmodule 56  57 /* 58 *(C) yf.x 2010  59 * 60 *Complier :Quartus II 9.1 61 *Filename :adder.v 62 *Description:A 8-bit adder,which support signed number in 2s complement. 63 *Release :06/30/2010 1.0 64 */ 65  66