等精度数字频率计的设计与仿真的毕业论文推荐.docVIP

PAGE 论文题目：等精度数字频率计设计与仿真 专业： 学生： 签名： 指导教师： 签名： 摘 要 本文主要介绍了在MAX+PLUSⅡ的仿真环境下，并基于VHDL程序语言的描述完成等精度数字频率计的设计与仿真，分为分频（fp）、位选(wx)、时钟(sz)、计数(countt)、译码显示(bcd7)共五个模块。在详细介绍了所设计的电路原理及对MAX+PLUSⅡ的软件概述后，开始整个设计过程。首先，实现将8Hz的系统时钟经16分频形成0.5Hz的基准时钟，即提供高电平为1s的计数周期；其次，将被测信号根据实际需求分频（可进行1、10、100、1000分频的选择），完成1Hz、10Hz、100Hz、1000Hz的不同档位选择；接着，在核心模块计数器的功能实现下完成对被测信号的频率测量；最后，在译码显示模块功能的实现下，将计数所得的4位二进制码转换成7位码显示输出。经过对仿真结果的分析，符合设计要求。 【关键词】 频率计 分频 MAX+PLUSⅡ VHDL 【论文类型】 应用型 Title: Equal Precision Frequency Meter Design and Simulation Major: Name: Signature: Supervisor: Signature: ABSTRACT The context mainly introduces the completion of the equal precision frequency meter design and simulation with the MAX+PLUSⅡ simulation environment and description of the VHDL language. The frequency meter includes five modules in total which are frequency division (fp)、selection (wx)、clock (sz)、count (countt) and decoding display (bcd7). After the detailed description of the designed circuit principle and the overview of MAX+PLUSⅡsoftware, the whole design process comes into being. First of all, 8Hz system clock will be converted into 0.5Hz reference clock by 16 frequency divided, i.e. providing the count period with 1s high level; next, the measured signal will have the frequency divided according to the actual needs (can select different divided frequency ,1、10、100、1000)，so that it could accomplish 1Hz、10Hz、100Hz、1000Hz，the different gear election; then, the completion of the function of the core module counter will complete the frequency measurement of the measured signal; finally, with the function realization of decoding display module, the 4 bit binary count code will be converted into 7 bit code that is for output display. Through the analysis of the simulation results, it matches the design requirement. 【Key words】Frequency Meter Frequency Divided MAX+PLUSⅡ VHDL 【Type of Thesis】Type of Applica