有限状态机进行时序逻辑的设计.docVIP

有限状态机进行时序逻辑的设计 一：有限状态机进行时序逻辑的源程序: module seqdet(x,z,clk,rst,state); input x,clk,rst; output z; output[2:0] state; reg[2:0] state; wire z; parameter IDLE=d0,A=d1,B=d2, C=d3,D=d4, E=d5,F=d6, G=d7; assign z=(state==Ex==0)?1:0; always@(posedge clk) if(!rst) begin state=IDLE; end else casex(state) IDLE:if(x==1) begin state=A; end A: if(x==0) begin state=B; end B: if(x==0) begin state=C; end else begin state=F; end C: if(x==1) begin state=D; end else begin state=G; end D: if(x==0) begin state=E; end else begin state=A; end E: if(x==0) begin state=C; end else begin state=A; end F: if(x==1) begin state=A; end else begin state=B; end G: if(x==1) begin state=F; end default: state=IDLE; endcase endmodule 二：有限状态机进行时序逻辑的测试代码： `timescale 1ns/1ns `include seqdet.v module tb_seqdet; reg clk,rst; reg[23:0] data; wire[2:0] state; wire z,x; seqdet tb_seqdet (x,z,clk,rst,state); assign x=data[23]; always #10clk=~clk; always@(posedge clk) data={data[22:0],data[23]}; initial begin clk=0; rst=1; #2 rst=0; #30 rst=1; data=b1100_1001_0000_1001_0100; #600 $stop; end initial $monitor($time,,,%d,%d,%d,x,z,state); endmodule 三：Transcript显示结果： # 0 x,x,x # 10 x,0,0 # 32 0,0,0 # 110 1,0,0 # 130 1,0,1 # 150 0,0,1 # 170 0,0,2 # 190 1,0,3 # 210 0,0,4 # 230 0,1,5 # 250 1,0,3 # 270 0,0,4 # 290 0,1,5 # 310 0,0,3 # 330 0,0,7 # 350 1,0,7 # 370 0,0,6 # 390 0,0,2 # 410 1,0,3 #