官方说明书IDT IDT71V3558SA Data Sheet.pdf

IDT IDT71V3558SA Data Sheet /file/2634287 From ManualL ManualL collects and classifies the global product instrunction manuals to help users access anytime and anywhere, helping users make better use of products. Home: / Chinese: / This Manual: /file/2634287 查询IDT71V3556S供应商 128K x 36, 256K x 18 IDT71V3556S 3.3V Synchronous ZBT SRAMs IDT71V3558S 3.3V I/O, Burst Counter IDT71V3556SA Pipelined Outputs IDT71V3558SA 128K x 36, 256K x 18 memory configurations The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega- Supports high performance system speed - 200 MHz bit) synchronous SRAMS. They are designed to eliminate dead bus (3.2 ns Clock-to-Data Access) cycles when turning the bus around between reads and writes, or TM TM ZBT Feature - No dead cycles between write and read writes and reads. Thus, they have been given the name ZBT , or cycles Zero Bus Turnaround. Internally synchronized output buffer enable eliminates the Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it need to