脉冲数据发生器数据产生模块设计-测试计量技术及仪器专业论文.docx

摘 要摘 要高性能脉冲/数据发生器作为通用数字信号源的典型代表在数据域测试仪器中 占有重要的地位，其功能就是产生各种数字激励信号波形或时序，并根据用户需 要任意配置这种波形或时序。鉴于高性能脉冲数据发生器在数据域测试中的重要性，结合电子科技大学承 担的“高性能脉冲/数据信号发生器”科研项目，本文围绕多模式下多码型高速串 行数据的产生方法展开研究，通过分析和比较各种技术，制定出串行数据产生和 延迟调整的解决方案。设计中，利用现场可编程门阵列（FPGA）作为整个模块电路的控制部分，通 过外部并串转换电路将低速的并行数据转换高速串行数据，实现连续模式、触发 模式和门控模式下串行数据信号的产生和多项参数的调节，大大简化了硬件设计 电路，获得了可编程性好、可靠程度高的高速数字信号。本文的主要工作包括：1. 完成系统方案的制定，硬件电路的设计和调试工作；2. 采用高性能低成本的 FPGA 实现多模式多码型数据的产生；3. 在 FPGA 控制下，利用高速并串转换电路实现将数据存储器输出的低速并 行数据转换为高速的串行数据流；4. 用计数器和高精度可编程延迟线组合的方法实现信号延迟。关键字：脉冲/数据发生器，数据产生，多模式，高速串行数据，延迟ABSTRACTABSTRACTAs a typical representative in universal digital signal source, high-performance pulse signal / pattern data generator plays a very important role in the digital testing equipment. Its function is to produce a variety of digital signal waveform or incentive timing, and configure the waveform and timing according to user’s needs.For high-performance pulse signal / pattern data generator is so important in digital testing domain and UESTC (University of Electronic Science and Technology of China) takes charge of the “High-performance pulse signal / pattern data generator project” research, this dissertation studies the generation of pattern data signals. Finally a proper solution is made to generate serial pattern data signals according to analyzing and comparing kinds of technologies.In this scheme, control module of the whole system is realized by Field Programmable Gate Array (FPGA). And the well-programmable and high-dependable digital signal stream under three modes is achieved by the technology of reading data from low-speed data memory and converting low-speed parallel data to high-speed serial ones by using the parallel to serial data converting circuit. The design has simplified the circuit design. The main work of this dissertation includes:Completing the block diagram design of the system, the circuit design and its debugging;Realizing the serial data output under three modes;Realizing high-speed serial data stream by converti