网站大量收购独家精品文档,联系QQ:2885784924

esca高性能处理器控制内核的分析与实现word格式论文.docx

esca高性能处理器控制内核的分析与实现word格式论文.docx

  1. 1、本文档共85页,可阅读全部内容。
  2. 2、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。
  3. 3、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  4. 4、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
查看更多
esca高性能处理器控制内核的分析与实现word格式论文

AbstractHybridcomputingarchitectureexploitsprocessorarchitectureadvantagestooptimize controlintensiveandcomputingintensivetasksindependentlybyequipmenting heterogeneousprocessors.Differentprocessorscooperatetoaccelerateapplications.Itis becommingoneofthekeytrendsofhighperformancecomputingarchitecture.Ourgroup hasdesignesahighperformancemulti-coreprocessor-ESCA(EngineeringandScientific ComputingAccelerator)to accelerate applications in scientific and multimedia fieldbaseon hybridcomputingtheory.ESCAProcessoraimsatacceleratingcomputingintensivetasks inapplicationsasacoprocessor.ItadoptsSIMD/Vector/Sub-wordtechnologytogainhigh performance.ESCAprocessorconsistsofcontrolcoreandcomputingfabric.Thispaperfocuseson research of key technology and implementationofthe control core.Firstly,thispaperintroducesmodelsrelatedtoESCAsystem.Secondly,itintroduces keypointsofESCAprocessorarchitecturesuchasISA,hardwareframeworkandmemory organizationetc.Baseonthisknowloge,itcanmakeclearofdetailfunctionsofthecontrol coreanddefineitsmicro-architecture.ThecontrolcoreadoptshierarchyISAcodingwith instructionextendingforspecialcontrolflow.Anewexplicitmemoryaccessmechanism alsohasbeenintroducesforoptimizationofmassiveregulardatatransmission.Asfor hardwareimplementation,ittakespipelineastheprinciplelineandkeepsbalancebetween performanceandspending.Complexcontrolflowincreasesdifficultyoffunction verification.Sothispapertakessoftwareandhardwareco-verificationmethod.Itdesigned andimplementedhybridverificationplatformforcontrolcore,takenautomateverification flowand shorten verification cyclelargely.Final ESCAprocessor design has been taped out.It works at 250MHz. The chip area is00μm2andthecontrolcorehastaken3107821.56μm2,about17.58%.Baseon ESCAsystem,wehaveevaluatedtheexplicitmemoryaccessmechanism.Resultsshow thatthehiddenofmemoryaccesslatencycanoccupy56%ofthetotalruntimeandachieve1.5timesspeedupwiththekernelofDGEMM,whichprovesthattheproposedmemory accessmechanismisbeneficialtofillthegapbet

您可能关注的文档

文档评论(0)

peili2018 + 关注
实名认证
内容提供者

该用户很懒,什么也没介绍

1亿VIP精品文档

相关文档