MODERN OPERATING SYSTEMS Third Edition ANDREW S TANENBAUM Chapter资料.ppt

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MODERN OPERATING SYSTEMS Third Edition ANDREW S TANENBAUM Chapter资料.ppt

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MODERN OPERATING SYSTEMS Third Edition ANDREW S TANENBAUM Chapter资料

Figure 11-27. Mapping of Win32 priorities to Windows priorities. Scheduling (3) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 Figure 11-28. Windows Vista supports 32 priorities for threads. Scheduling (4) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 Figure 11-29. An example of priority inversion. Scheduling (5) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 Memory Management(1) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 Figure 11-30. Virtual address space layout for three user processes on the x86. The white areas are private per process. The shaded areas are shared among all processes. Figure 11-30. Virtual address space layout for three user processes on the x86. The white areas are private per process. The shaded areas are shared among all processes. Memory Management (2) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 Figure 11-30. Virtual address space layout for three user processes on the x86. The white areas are private per process. The shaded areas are shared among all processes. Memory Management (3) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 Figure 11-31. The principal Win32 API functions for managing virtual memory in Windows. Addressing Large Physical Memories Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 Figure 11-32. Mapped regions with their shadow pages on disk. The lib.dll file mapped into two address spaces at same time. Implementation of Memory Management Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 Figure 11-33. A page table entry (PTE) for a mapped page on the (a) Intel x86 and (b) A