CPLD实现组合电路.pptVIP

CPLD实现组合电路 实验目的 学习用Verilog HDL编程实现组合逻辑电路的方法 学习Verilog HDL的结构描述、数据流描述和行为描述方式 学习Xilinx ISE软件的使用 了解Fit Report中的参数对编程的指导意义 实验器材 PC机 Xilinx ISE软件 001181092-Xilinx实验仪 实验内容 一、结构描述方式实现七段译码显示 二、结构数据流方式实现七段译码显示 三、行为描述方式(逻辑代数代入)实现七段译码显示 四、行为描述方式(case 语句)实现七段译码显示 五、分别运行Fit Report，比较不同代码资源消耗情况 一、结构描述方式实现七段译码显示 module strushow(key, seg7led, bit4sel); input [3:0] key; output [7:0] seg7led; ____________________; wire w1x1x, w11xx, wxx11, wx01x, wx110, wx101, wx010, wx111, wx100, wx001, w00x1, w000x, w0001; _______________; not not0(nky[0], key[0]); not not1(nky[1], key[1]); ________________________; not not3(nky[3], key[3]); and and1x1x(w1x1x, key[3], key[1]); and and11xx(w11xx, key[3], key[2]); __________________________________; and andx01x(wx01x, nky[2], key[1]); and andx110(wx110, key[2], key[1], nky[0]); __________________________________________; and andx010(wx010, nky[2], key[1], nky[0]); and andx111(wx111, key[2], key[1], key[0]); __________________________________________; and andx001(wx001, nky[2], nky[1], key[0]); and and00x1(w00x1, nky[3], nky[2], key[0]); __________________________________________; and and0001(w0001, nky[3], nky[2], nky[1], key[0]); nor nora(seg7led[0], w0001, w1x1x, wx110, wx100); nor norb(seg7led[1], w1x1x, wx110, wx101); __________________________________; nor nord(seg7led[3], wx111, wx100, wx001); nor nore(seg7led[4], wx101, wx100, key[0]); ____________________________; nor norg(seg7led[6], w000x, wx111); assign bit4sel=4b0; endmodule 二、结构数据流方式实现七段译码显示 module flowshow(key, seg7led, bit4sel); input [3:0] key; ______________; output [3:0] bit4sel; wire w1x1x, w11xx, wxx11, wx01x, wx110, wx101, wx010, wx111, wx100, wx001, w00x1, w000x, w0001; _______________; assign nky[0] = ~ key[0]; ________________________; assign nky[2] = ~ key[2]; assign nky[3] = ~ key[3]; assign w1x1x = key[3] key[1]; ______________________________; assign wxx11 = key[1] key[0]; assign wx01x = nky[2] key[1]; _______________________________________; ass