数字电路设计课件第四讲VHDL的基本的 功能描述语句.pptVIP

第四讲;构造体;并行语句;并行语句;Begin End;直接信号赋值语句;例：4 选 1 数据选择器 Architecture a of mux4_1 is Begin x = (a AND NOT(s(1)) AND NOT(s(0))) OR (b AND NOT(s(1)) AND s(0)) OR (c AND s(1) AND NOT(s(0))) OR (d AND s(1) AND s(0)) ; End a;;例： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY test is PORT( A,B,C : IN Std_Logic; D,E : OUT Std_Logic ); END test;;ARCHITECTURE a OF test IS BEGIN D = A and B; E = not C; END a;;条件信号赋值语句( When_Else );When_Else语句举例(1);条件信号赋值语句( When_Else );When_Else语句举例(2);选择信号赋值语句(With_Select_When);With_Select_When语句举例（1）;选择信号赋值语句( With_Select_When );With_Select_Then语句举例（2）;构造体结构图;进程语句;进程语句;进程语句;LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY if_case IS PORT ( a, b, c, d : IN Std_Logic; sel : IN Std_Logic_Vector(1 downto 0); y, z : OUT Std_Logic); END if_case; ARCHITECTURE logic OF if_case IS BEGIN if_label: PROCESS(a, b, c, d, sel) BEGIN IF sel=00 THEN y = a; ELSIF sel=01 THEN y = b; ELSIF sel=10 THEN y = c; ELSE y = d; END IF; END PROCESS if_label;;信号敏感表;敏感表举例;敏感表举例;顺序语句;顺序赋值语句举例(1);顺序赋值语句举例(1);顺序赋值语句举例(2);D;顺序赋值语句举例(2);D;顺序赋值语句举例(2);D;在时序电路中的变量赋值;IF_THEN_ELSE语句 ——流程控制语句（1）;IF 条件句 Then 顺序语句 END IF;IF_THEN_ELSE语句举例（1）;IF_THEN_ELSE语句举例（2）;library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity counter_4 is port ( clk: in STD_LOGIC; reset: in STD_LOGIC; ce: in STD_LOGIC; load: in STD_LOGIC; dir: in STD_LOGIC; din: in STD_LOGIC_VECTOR (3 downto 0); qout: buffer STD_LOGIC_VECTOR (3 downto 0) ); end counter_4;;architecture behavioral of counter_4 is begin process (clk,reset) begin if reset =1 then qout = (others=0); elsif CLKevent and CLK=1 then if load=1 then qout=din; else if ce=1 then if dir = 1 then; qout = qout +1; else qout = qout - 1; end if; end if; end if;