一个 12位100兆采样频率数模转换器设计.pdfVIP

摘要 摘要 本文设计的是一个采用 1.8v供电电压的 12位，100兆采样速率电流型DAC。 为了获得高的线性度和无杂闪动态范围（SFDR ），电路采用了高 7 位温度计译 码，低 5 位二进制译码的分割结构。由于设计的 DAC 每增加 1 位，电流源阵列 中的总晶体管面积增加四倍以使晶体管匹配满足精度要求，另外，连线和额外的 电路开销也会增加一倍，因此，单元阵列有几百微米的纬度，这使得要减小由于 工艺，温度和电学梯度引起的不匹配变得十分困难。为了解决这一问题，本文采 用 CSA 的方法，即电流源单独放在一个与其它电路分开来的阵列中。这种方法 使得电流源晶体管能被分成很多股放置在 CSA 中的不同地方以抵消梯度的影 响。另外，如果一股等于 1LSB，则温度计译码的 MSB 和二进制译码的 LSB 之 间的缩放误差可以被消除。然而，为了抵消温度计译码的电流源晶体管的梯度， 各股晶体管之间的连线及整个 CSA 和其它电路之间连线会随着分割程度的增加 而急剧增加。 关键词——数模转换器（DAC），分割结构，温度计译码，二进制译码，电 流源阵列（CSA ），匹配 1 Abstract Abstract A 12-bit 320-MSample/s current-steering D/A converter with the supply voltage of 1.8-v is presented. In order to achieve high linearity and spurious free dynamic range (SFDR), a large degree of segmentation has been used, with the seven most significant bits (MSBs) being implemented as equally weighted current sources. As for each extra bit of accuracy, the gate-area of the current source transistors in the cell matrix must increase by a factor of 4 so that the transistor matching is within the desired accuracy. In addition, the area overhead due to the interconnect lines and the additional circuitry roughly doubles. As consequence, the cell matrix has dimensions of several hundred microns, and it becomes increasingly difficult to minimize the impact of the systematic mismatch sources on the DAC accuracy due to process, temperature, and electric gradients. To solve this problem, this design used the CSA approach, in which the current sources alone are laid out in an array separated from the rest of the circuitry which is then laid out in a bit slice fashion. This approach has the advantage that the current-sour