基于VHDL硬件描述语言篮球比赛计时器设计与仿真.doc

武汉工程大学邮电与信息工程学院 毕业设计（ 论 文 ）说明书 论文题目 基于VHDL硬件描述语言的篮球比赛计时器的设计与仿真 学 号 学生姓名 专业班级 指导教师 总评成绩 年 月 日 摘 要 随着EDA技术的高速发展，VHDL硬件描述语言作为硬件电路设计的一种重要工具成为现代高科技社会的一个闪亮标志。VHDL发展的目的是为了将电子电路的设计和内部的含义用文件的方式存储起来，以便其他人能够轻易地了解电路的设计意义。这也就是说设计电路可以通过文子描述的方式完成设计工作，电子电路也可以当做文件一样来存储。VHDL主要用于描述数字系统的结构，行为，功能和接口。除了含有许多具有硬件特征的语句外，VHDL的语言形式和描述风格与句法是十分类似于一般的计算机高级语言。Abstract With the rapid development of EDA technology, VHDL hardware description language hardware circuit design as an important tool for modern high-tech society has become a shining symbol. VHDL is designed for the development of electronic circuit design and the meaning of the internal use of papers stored so that other people can easily understand the meaning of circuit design. That is to say the design of the circuit can be described by way of sub-text to complete the design work, the electronic circuit can also be the same as a file to store. VHDL description of digital systems primarily for the structure, behavior, functions and interfaces. In addition to containing many features of the statement outside the hardware, VHDL description of the language forms and style and syntax are very similar to the general high-level language computer.  This thesis describes VHDL hardware description language based on the basketball game timer basic principles, composition and design, procedures for compiling, with the MAX + plus II simulation software and other related technologies. First of all, the design of the timer into the top and the bottom two parts, divided at the bottom in a number of modules and procedures were designed, and finally the use of MAX + plus II simulation software debugging. Key words：basketball game timer module MAX+plus II simul