数字逻辑精品教学资料(华南理工大学)3-logic gates and level.pptVIP

数字逻辑精品教学资料(华南理工大学)3-logic gates and level.ppt

  1. 1、原创力文档(book118)网站文档一经付费(服务费),不意味着购买了该文档的版权,仅供个人/单位学习、研究之用,不得用于商业用途,未经授权,严禁复制、发行、汇编、翻译或者网络传播等,侵权必究。。
  2. 2、本站所有内容均由合作方或网友上传,本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺!文档内容仅供研究参考,付费前请自行鉴别。如您付费,意味着您自己接受本站规则且自行承担风险,本站不退款、不进行额外附加服务;查看《如何避免下载的几个坑》。如果您已付费下载过本站文档,您可以点击 这里二次下载
  3. 3、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等,请点击“版权申诉”(推荐),也可以打举报电话:400-050-0827(电话支持时间:9:00-18:30)。
  4. 4、该文档为VIP文档,如果想要下载,成为VIP会员后,下载免费。
  5. 5、成为VIP后,下载本文档将扣除1次下载权益。下载后,不支持退款、换文档。如有疑问请联系我们
  6. 6、成为VIP后,您将拥有八大权益,权益包括:VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
  7. 7、VIP文档为合作方或网友上传,每下载1次, 网站将根据用户上传文档的质量评分、类型等,对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档
查看更多
* xy+xz+yz LLLH LHHH Copyright ? 2007 Elsevier Copyright ? 2007 Elsevier 1-* Digital Logic Topic: Logic gates and Level 1-* Logic Gates Perform logic functions: inversion (NOT), AND, OR, NAND, NOR, etc. Single-input: NOT gate, buffer Two-input: AND, OR, XOR, NAND, NOR, XNOR Multiple-input 1-* Truth Tables Provides a listing of every possible combination of values of binary inputs to a digital circuit and the corresponding outputs. Digital circuit inputs outputs x y x + y x . y x y x . y x + y 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 1 Example (2 inputs, 2 outputs): inputs outputs Truth table 1-* Single-Input Logic Gates 1-* Two-Input Logic Gates 1-* More Two-Input Logic Gates 1-* Multiple-Input Logic Gates 1-* Logic Levels Define discrete voltages to represent 1 and 0 For example, we could define: 0 to be ground or 0 volts 1 to be VDD or 5 volts But what if our gate produces, for example, 4.99 volts? Is that a 0 or a 1? What about 3.2 volts? 1-* Logic Levels Define a range of voltages to represent 1 and 0 Define different ranges for outputs and inputs to allow for noise in the system Noise is anything that degrades the signal For example, a gate (driver) could output a 5 volt signal but, because of losses in the wire and other noise, the signal could arrive at the receiver with a degraded value, for example, 4.5 volts 1-* Logic Levels 1-* Noise Margins NMH = VOH – VIH NML = VIL – VOL 1-* The Static Discipline Logic Family VDD VIL VIH VOL VOH TTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4 CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84 LVTTL 3.3 (3 - 3.6) 0.8 2.0 0.4 2.4 LVCMOS 3.3 (3 - 3.6) 0.9 1.8 0.36 2.7 1-* Logic Gates: The Inverter The Inverter A A A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Ground Vcc Top View of a TTL 74LS family 74LS04 Hex Inverter IC Package Truth table 1-* Logic Gates: The AND Gate A B A.B Truth table 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Ground Vcc Top View of a TTL 74LS family 74LS08 Quad 2-input AND Gate IC Package The AND Gate 1-* L

文档评论(0)

1243595614 + 关注
实名认证
文档贡献者

文档有任何问题,请私信留言,会第一时间解决。

版权声明书
用户编号:7043023136000000

1亿VIP精品文档

相关文档