DDR引起Desense案例探讨.pdfVIP

1 Issue  As shown below, for DDR, the CLK frequency is half of data frequency. So, desense is seen on channels surrounding (533/ 2 * 7 = DCS 1800 ; 533/2 *8 =W/L-B1) when DDR is running at 533 MHz[1-3].  And channels surrounding (400/2 * 9, = DCS 1800 ; 400/2 * 10 = 2000 MHz, right above the high band of PCS 1900 and W/L-B2) when DDR is running at 400 MHz[1-2]. (533/2)*N (533/2)*(N+1) (400/2)*N (400/2)*(N+1) Level 2 Channel Issue  In some design, DDR chip is on baseband chip(POP- Package on Package), DDR noise is coupled to baseband chip, noise then transfers to baseband chip RX I/Q pins and is carried to RF chip[1-2]. DDR Noise RX IQ BaseBand Transceiver Chip 3 Mitigation  Locate a LC filter near baseband chip on RX I/Q signal[1,2].  Nevertheless, the shunt capacitor should NOT be too large. DDR Noise RX IQ BaseBand Transceiver Chip 4 Mitigation  As show below, the wider the LTE signal bandwidth is, the wider the baseband I/Q signal bandwidth will be.  Take 150 pF shunt capacitor for example, chances are that the sensitivity of 15/20 MHz bandwidth LTE signal may degrade because I/Q signal is attenuated. 5 Reference [1]