毕业论文外文翻译-高速数字混锁相环频率合成器.doc

锁相技术译文翻译 英文原名：High Speed Digital Hybrid PLL Frequency Synthesizer 译文：高速数字锁相环频率合成器 英文 中文 High Speed Digital Hybrid PLL Frequency Synthesizer Abstract：The conventional PLL(Phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL (DH-PLL) which includes the open loop structure into the conventional PLL synthesizer has been studied to overcome this problem. It operates in high speed, but the hardware complexity and power consumption are other serious problems since the DLT (digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO (voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit makes the negligible overshoot and much shorter settling time for the ultra fast switching speed. Also, the hardware complexity and power consumption get decreased to about 28%, compared with the conventional DH-PLL. Key Words: PLL, DLT, Frequency synthesis INTRODUCTION High speed frequency synthesis is very important and is widely used in the electronic and communication system applications. In 1999, El-Ela proposed that additional signal which is a synchronized saw-tooth waveform from the D/A converter is injected into the VCO input of the conventional PLL frequency synthesizer for the high speed operation [1]. However, it needs the optimal slope and duration at every frequency synthesis. To get the high-speed, it is necessary to prepare the precise synchronization of the complicated design. In 2001, H. G. Ryu proposed a simplified structure of the DDFS (direct digital frequency synthesizer)-driven PLL for the high switching speed [2]. However, there is a problem that the speed of the whole system is limited by PLL. Y. Fouzar proposed a PLL frequency synthesizer of dual loop configuration using frequency-to-voltage conver