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EE 457 Syllabus Handout Fall 2010 Instructor: Gandhi Puvvada
Computer Systems Organization
Computer Systems Organization
1. Abstract: This course covers computer organization and design. It provides CS/CE/EE students
a substantial understanding of a CPU at its logic design level. Design of the control unit and the
data path unit of a simple multi-clock-cycle CPU and a pipelined CPU is covered in detail.
Hardware support for exceptions, dynamic scheduling of instructions (Tomasulo algorithm to
execute instructions in an out-of-order fashion), and branch prediction are also discussed.
Computer arithmetic and memory hierarchies (cache, main memory, virtual memory) are also covered.
Hardware-software interface is discussed. Students design in Verilog and use ModelSim simulator to
verify their design/simulation exercises.
At the end of the course, students are expected to feel confident to perform logic design of a CPU
or any hardware system utilizing pipelining and other RTL techniques and proceed to graduate courses
in computer architecture or general hardware design.
2. Course administration
a) Course prerequisites: EE201L Introduction to Digital
Circuits and EE357 Basic Organization
of Computer Systems are the necessary prerequisites.
Undergraduate students without these prerequisites will
not be able to do this course. Graduate students are
expected to have taken a logic design course and a
course covering some assembly language in their
undergraduate course work before taking this
course.
b) Classes: /academics/classes/term_20103/classes/ee.html
Lec 30604R 05:00-06:20pmMWPuvvada ZHS252
Lec 30568R 12:30-01:50pmTTh Puvvada ZHS252
Lec 30567R 03:30-04
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