Ringing Reduction Techniques for印制技术.pdfVIP

Application Report SLPA010 – November 2011 Ringing Reduction Techniques for NexFETTM High Performance MOSFETs ABSTRACT The design of switching converters with high performance MOSFET’s such as those found in the NexFETTM product line require special attention to detail to maximize the effectiveness of the devices and optimize the overall performance of the switching function. Consideration of the challenges of working with ultra-fast power devices early in the design process will ensure the highest performing, most reliable final product. In this Application Note, the Power Stage of the typical Non-Isolated Synchronous Buck Converter (see Figure 1) will be used as a reference for discussing practical design considerations for maximizing the performance and lifetime of NexFET products. The most common problem encountered in this scenario is parasitic Voltage Ringing superimposed on the rising edge of the Switch Node. This Application Note will discuss the source of the switch node ringing, measurement techniques to accurately characterize this ringing, and methods for minimizing the effect while maintaining excellent system performance. Backgound Figure 1 shows the schematic of a typical synchronous buck converter. As the performance of power devices is improved, the control FET has the ability to switch voltages at rates greater than 10kV/µs. However, the fast switching faces a common challenge of dealing with switching noise. In particular when the Control FET turns on and the Sync FET is off, the loop inductor, the loop resistor and the output capacitor of the