应用VHDL引用LPM库的设计32位加法器.doc

课程名称 EDA 学 院 电 信 专 业 电 信 班 级 三 班 学 号 姓 名 指导老师  目录 第一章、 题目..........................................3 第二章、 设计步骤......................................4 第三章、 设计心得.....................................40 第四章、 参考文献.....................................41 题目 应用VHDL引用LPM库设计32位加法器。 要求在Quartus II软件，利用VHDL完成层次式电路设计，电路中的元件可以用VHDL设计也可以用库元件连线构成再封装。借助EDA工具中的综合器，适配器，时序仿真器和编程器等工具进行相应处理。输入方法不限制。适配元件不限制。要求综合出RTL电路，并进行仿真输入波形设计并分析电路输出波形。 设计步骤 新建工程输入设计项目并存盘： 利用lpm_add_sub函数。 参数设定： 引脚分配： 程序清单： OPTIONS NAME_SUBSTITUTION = ON; INCLUDE addcore; INCLUDE look_add; INCLUDE bypassff; INCLUDE altshift; INCLUDE alt_stratix_add_sub; INCLUDE alt_mercury_add_sub; PARAMETERS ( LPM_WIDTH, LPM_REPRESENTATION = SIGNED, LPM_DIRECTION = DEFAULT, -- controlled by add_sub port ONE_INPUT_IS_CONSTANT = NO, LPM_PIPELINE = 0, MAXIMIZE_SPEED = 5, REGISTERED_AT_END = 0, OPTIMIZE_FOR_SPEED = 5, USE_CS_BUFFERS = 1, CARRY_CHAIN = IGNORE, CARRY_CHAIN_LENGTH = 32, DEVICE_FAMILY, USE_WYS = OFF, STYLE = NORMAL, CBXI_PARAMETER = NOTHING ); INCLUDE aglobal90.inc; % device family definitions % FUNCTION @CBXI_PARAMETER (aclr, add_sub, cin, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1. RETURNS (cout, overflow, result[LPM_WIDTH-1..0]); -- a useful macro DEFINE MIN(a, b) = a b ? a : b; -- LPM_PIPELINE became the new name for LATENCY. Will keep LATENCY in the code. CONSTANT LATENCY = LPM_PIPELINE; -- Determine the effective speed (vs. size) optimization factor: If The local -- param is used, take it as the effective value, otherwise use the global value CONSTANT SPEED_MAX_FACTOR = USED(MAXIMIZE_SPEED) ? MAXIMIZE_SPEED : OPTIMIZE_FOR_SPEED; -- Internal and external latency CONSTANT LAST_STAGE_INDEX = (REGISTERED_AT_END == 1) ? 1 : 0; CONSTANT INT_STAGES_NUM = LATENCY + 1 - LAST_STAGE_INDEX; CONSTANT