VHDL16路抢答器.docVIP

鉴别模块的设计与实现 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY LCQDJB IS PORT (CLR: IN STD_LOGIC; CLK: IN STD_LOGIC; G1,G2,G3,G4,G5,G6,G7,G8,G9,G10,G11,G12,G13,G14,G15,G16: IN STD_LOGIC; X: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)); END ; ARCHITECTURE ART OF LCQDJB IS BEGIN PROCESS (CLR,G1,G2,G3,G4,G5,G6,G7,G8,G9,G10,G11,G12,G13,G14,G15,G16) BEGIN IF CLR=1 THEN X=00000; IF G1=1 AND G2=1 AND G3=1 AND G4=1 AND G5=1 AND G6=1 AND G7=1 AND G8=1 AND G9=1 AND G10=1 AND G11=1 AND G12=1 AND G13=1 AND G14=1 AND G15=1 AND G16=1 THEN X = 00000; ELSIF G1=0 THEN X = 00001; ELSIF G2=0 THEN X = 00010; ELSIF G3=0 THEN X = 00011; ELSIF G4=0 THEN X = 00100; ELSIF G5=0 THEN X = 00101; ELSIF G6=0 THEN X = 00110; ELSIF G7=0 THEN X = 00111; ELSIF G8=0 THEN X = 01000; ELSIF G9=0 THEN X = 01001; ELSIF G10=0 THEN X = 01010; ELSIF G11=0 THEN X = 01011; ELSIF G12=0 THEN X = 01100; ELSIF G13=0 THEN X = 01101; ELSIF G14=0 THEN X = 01110; ELSIF G15=0 THEN X = 01111; ELSIF G16=0 THEN X = 10000; END IF; END IF; END PROCESS; END; 原理：第一个按下键的小组，抢答信号判定电路QDJB通过缓冲输出信号的反馈将本参赛组抢先按下按键的信号锁存，并且以异步清零的方式将其他参赛组的锁存器清零，组别显示、计时和计分会保存到主持人对系统进行清零操作时为止。当CLR=1时系统复位，使组别显示信号X=00000，G1=1 G2=1 G3=1 G4=1 G5=1 G6=1 G7=1 G8=1 ‘G9=1 G10=1 G11=1 G12=1G13=1 G14=1 G15=1 G16=1 当CLR=0，即低电平有效，使其进入抢答鉴别状态，到CLK的上升沿到来时，以A组抢答成功为例，当输入信号为G1=0 G2=1 G3=1 G4=1 G5=1 G6=1 G7=1 G8=1 ‘G9=1 G10=1 G11=1 G12=1G13=1 G14=1 G15=1 G16=1输出信号X=00001，A1=1，即为鉴别出1组抢答成功，同时屏蔽其他组的输入信号，以免发生错误。同理其他组别抢答成功也是这样的鉴别过程。【9】 译码显示模块 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY LCYMQ IS PORT (YM: IN STD_LOGIC_VECTOR(4 DOWNTO 0); DM: OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END ; ARCHITECTURE ART OF LCYMQ IS BEGIN PROCESS (YM) BEGIN CASE YM IS WHEN 00000 = DM = 0