CPLDFPA实验台设计.doc

摘 要 本系统中主要运用了电路编辑、VHDL语言来设计，并配合Altera公司的MAX+PLUSII软件进行仿真调试，该软件完全集成化，易学易用，它可以在多种平台上运行。 在设计本系统时，将其分解为若干个子系统。子系统再分解为一个个功能独立的模块，这些模块经过设计、仿真、功能正确后，像拼积木似的根据需要进行不同的拼接，完成特定的功能。 运用可编程逻辑器件，是不仅能在短时间里完成计划任务，而且能使系统的速度更快，体积更小，重量更轻，功耗更少，加密性能更可靠，满足现代电子发展的需要。 本系统主要设计的是键盘扫描电路，数码显示电路，A/D、D/A控制器电路，然后运用可编程逻辑器件进行硬件验证。 关键词： VHDL 模块 仿真 Abstract This system make use of primarily the electric circuit edits, the language of VHDL to design, and match with the company of Altera MAX+PLUSII software proceeds to imitate to really adjust to try, that software gathers completely, is easy to be learned and used easily, it can run on various platform. While designing the system, it is septrated from some sub-system. The sub-system resolves to an again independent mold in function in each piece, these moldses piece through design, imitate true, function right empress, resemble put together the wooden blocks according to need to be proceeded to put together to connect differently, complete the particular function. The programmable logic in application apparatus can not only complete to plan the mission within short time, but also can make system speed is sooner, the physical volume is smaller, the weight is lighter, the power is less, encrypt the function is more dependable.it satisfy the demand of the modern electronics development. This system designs primarily is a keyboard to scan the electric circuit, number display, A/ D, D/ A controller circuit, then we make use of the programmable logic apparatus which proceeding the hardware the verification. Key words: VHDL, Module, Really- Imitate 目 录 第一章绪论…………………………………………………………………1 1.1引言…………………………………………………………………1 第二章VHDL语言的概述…………………………………………………3 2.1VHDL语言的概述……………………………………………………3 2.2VHDL语言特性………………………………………………………3 2.3VHDL语言的基本结构………………………………………………4 第三章EPM7128S芯片简介………………………………………………5 第四章CPLD/FPGA实验平台设计……………………………………7 4.1CPLD实验平台功能概述…………………………………………7 4.2CPLD实验平台功能模块及VHDL程序设计说明……………………8 4.2.1键盘显示VHDL程序设计…………………………………………8 4.2.2A